Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)

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概要

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• It was found that the etch rate of Si in tetramethylammonium hydroxide (TMAH) solution is significantly retarded by introducing ion implantation damage. By utilizing this new phenomenon, i.e., ion-bombardment-retarded etching (IBRE) of Si, a novel process to fabricate an ultrathin Si channel wall for the vertical double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) was developed. We succeeded in fabricating a vertical Si wall with thickness of 16 nm on bulk Si substrate with no introduction of dry etching damage. The effectiveness of thinning the Si channel wall to the characteristics of a vertical DG MOSFET was examined by means of simulations.

• 2003-04-15

著者

• Ohdomari Iwao

  School Of Science And Engineering Waseda University

• Tanii Takashi

  School Of Science And Engineering Waseda University

• Kanemaru Seigo

  Nanoelectronics Research Institute Aist

• Masahara Meishoku

  Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology

• Suzuki Eiichi

  Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology

• Liu Yongxun

  Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology

• Tanoue Hisao

  Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology

• Nagao Masayoshi

  Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology

• Matsukawa Takashi

  Nanoelectronics Research Institute Aist

• Ishii Kenichi

  Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology (aist)

• Masahara Meishoku

  Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

• Matsukawa Takashi

  Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

• Suzuki Eiichi

  Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

• Ishii Kenichi

  Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

• Ishii Kenichi

  Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

• Tanoue Hisao

  Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

• Tanii Takashi

  School of Science and Engineering, Waseda University, 3-4-1 Ohkubo, Shinjuku, Tokyo 169-8555, Japan

• Kanemaru Seigo

  Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

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