A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching
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概要
- 論文の詳細を見る
A novel process for the fabrication of a gated silicon field emitter array is proposed. The process involves complete self-alignment of gate electrodes taking advantage of ion bombardment retarded etching. The ion-irradiated regions serve as masks for subsequent silicon etching resulting in the formation of tabletop structures. The structures are suitable for both the formation of pyramidal emitters and the arrangement of gate electrodes adjacent to each emitter. We integrate this silicon etching into a self-align process for the fabrication of gated emitter array. The emission characteristics of 100 emitters are tested, and the emission at a gate voltage of 30 V is detected. The results indicate that the proposed process is applicable to the fabrication of gated silicon emitters.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 2005-07-15
著者
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Matsuya Iwao
Kagami Memorial Laboratory For Materials Science And Technology Waseda University
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Ohdomari Iwao
School Of Science And Engineering Waseda University
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Tanii Takashi
School Of Science And Engineering Waseda University
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Numao Yoshiteru
School Of Science And Engineering Waseda University
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Sakairi Mitsuaki
School Of Science And Engineering Waseda University
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Masahara Meishoku
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Fujita Satoru
School Of Information Science Japan Advanced Institute Of Science And Technology
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Matsuya Iwao
Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishi-Waseda, Shinjuku, Tokyo 169-0051, Japan
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Numao Yoshiteru
School of Science and Engineering, Waseda University, 3-4-1 Ohkubo, Shinjuku, Tokyo 169-8555, Japan
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Fujita Satoru
School of Science and Engineering, Waseda University, 3-4-1 Ohkubo, Shinjuku, Tokyo 169-8555, Japan
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