A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching

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概要

• 論文の詳細を見る
• 2005-07-15

著者

• Matsuya Iwao

  Kagami Memorial Laboratory For Materials Science And Technology Waseda University

• TANII Takashi

  School of Science and Engineering, Waseda University

• FUJITA Satoru

  School of Science and Engineering, Waseda University

• NUMAO Yoshiteru

  School of Science and Engineering, Waseda University

• SAKAIRI Mitsuaki

  School of Science and Engineering, Waseda University

• MASAHARA Meishoku

  Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology

• OHDOMARI Iwao

  School of Science and Engineering, Waseda University

• Tanii Takashi

  School Of Science And Engineering Waseda University

• Numao Yoshiteru

  School Of Science And Engineering Waseda University

• Ohdomari Iwao

  Faculty Of Science And Engineering Waseda University

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• A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching

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