Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)
スポンサーリンク
概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-04-30
著者
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TANII Takashi
School of Science and Engineering, Waseda University
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MASAHARA Meishoku
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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OHDOMARI Iwao
School of Science and Engineering, Waseda University
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MATSUKAWA Takashi
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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ISHII Kenichi
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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SUZUKI Eiichi
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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Kanemaru Seigo
Nanoelectronics Research Institute Aist
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LIU Yongxun
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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NAGAO Masayoshi
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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TANOUE Hisao
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology
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Matsukawa Takashi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Liu Yongxun
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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