Ta/Mo Stack Dual Metal Gate Technology Applicable to Gate-First Processes
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概要
- 論文の詳細を見る
Dual metal gate technology using a combination of Mo and a Ta/Mo stack suitable for fully depleted silicon-on-insulator (FD-SOI) and double-gate (DG) transistors applicable to a gate-first process has been investigated. The annealing of the Ta/Mo stack at 600–700 °C induces the diffusion of Ta into the Mo layer, and different work functions between the single Mo layer and Ta/Mo stack gates are successfully obtained. The sputtered Mo gate exhibits a higher thermal stability than the e-beam-evaporated Mo gate. The difference in flatband voltage (0.31 V) between the Mo and Ta/Mo gates is ensured even after annealing at 850 °C for 20 s, by which subsequent source/drain activation can be carried out.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-04-30
著者
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Yamauchi Hiromi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Masahara Meishoku
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Suzuki Eiichi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Liu Yongxun
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Tsukada Junichi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Matsukawa Takashi
Nanoelectronics Research Institute Aist
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Ishii Kenichi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology (aist)
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Endo Kazuhiko
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology (aist)
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Tsukada Junichi
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Yamauchi Hiromi
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Masahara Meishoku
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Liu Yongxun
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Matsukawa Takashi
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Suzuki Eiichi
Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Ishii Kenichi
Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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