Atomic Layer Deposition of SiO₂ for the Performance Enhancement of Fin Field Effect Transistors
スポンサーリンク
概要
著者
-
Ishikawa Yuki
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
-
Yamauchi Hiromi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
-
Sakamoto Kunihiro
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
-
Masahara Meishoku
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
-
Liu Yongxun
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
-
Tsukada Junichi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
-
Matsukawa Takashi
Nanoelectronics Research Institute Aist
-
Endo Kazuhiko
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology (aist)
-
Masahara Meishoku
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki 305-8568, Japan
-
Matsukawa Takashi
Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki 305-8568, Japan
関連論文
- Enhancing Noise Margins of Fin-Type Field Effect Transistor Static Random Access Memory Cell by Using Threshold Voltage-Controllable Flexible-Pass-Gates
- New Fabrication Technology of Fin Field Effect Transistors Using Neutral-Beam Etching
- Fabrication of a Vertical-Channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor Using a Neutral Beam Etching
- FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction
- Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)
- Investigation of N-Channel Triple-Gate MOSFETs on (100) SOI Substrate
- Behaviors of surfactant atoms on Si(001) surface
- Mechanism of Tungsten Plug Corrosion during Chemical Stripping Process : Scanning Maxwell-Stress Microscopy and Electrochemical Potentiometry Studies
- Demonstration of Dopant Profiling in Ultrathin Channels of Vertical-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect-Transistor by Scanning Nonlinear Dielectric Microscopy
- Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)
- Novel Process for Vertical Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) Fabrication
- A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology
- High-Frequency Precise Characterization of Intrinsic FinFET Channel
- A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology
- Device Design Consideration for $V_{\text{th}}$-Controllable Four-Terminal Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor
- Dual-Metal-Gate Transistors with Symmetrical Threshold Voltages Using Work-Function-Tuned Ta/Mo Bilayer Metal Gates
- Ta/Mo Stack Dual Metal Gate Technology Applicable to Gate-First Processes
- P-Channel Vertical Double-Gate MOSFET Fabricated by Utilizing Ion-Bombardment-Retarded Etching Processs
- Demonstration and Analysis of Accumulation-Mode Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor
- A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching
- Programmable Conductivity of Silicon Nanowires with Side Gates by Surface Charging
- Atomic Layer Deposition of SiO
- Atomic Layer Deposition of SiO₂ for the Performance Enhancement of Fin Field Effect Transistors