Programmable Conductivity of Silicon Nanowires with Side Gates by Surface Charging
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概要
- 論文の詳細を見る
Silicon nanowires with programmable conductivity which utilized sensitivity of conductance to surface charging have been investigated in terms of complementary operation of p- and n-type devices. The device fabricated from a silicon-on-insulator (SOI) wafer consists of a nanowire (width $\approx$ 30 nm) and side gates for control of surface charging onto the nanowire. The wire current clearly exhibited hysteresis by sweeping the side gate voltage at a constant rate. The transistor characteristics obtained using the SOI substrate as a back gate also exhibited programmable threshold voltage by applying a pulse bias to the side gate. Surface potential imaging of the nanowire by means of scanning Maxwell-stress microscopy (SMM) has been carried out for correlating the programmability to surface charging. The SMM images clearly explained the origin of the programmability and the complementary operation of the p- and n-type nanowires.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-04-15
著者
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Kanemaru Seigo
Nanoelectronics Research Institute Aist
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Itoh Junji
Nanoelectronics Research Institute Aist
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Masahara Meishoku
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Tanoue Hisao
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Nagao Masayoshi
Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology
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Matsukawa Takashi
Nanoelectronics Research Institute Aist
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Masahara Meishoku
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Nagao Masayoshi
Nanoelectronics Research Institute, AIST, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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