Yamauchi Hiromi | Nanoelectronics Research Institute National Institute Of Advanced Industrial Science And Technology

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著作論文

Enhancing Noise Margins of Fin-Type Field Effect Transistor Static Random Access Memory Cell by Using Threshold Voltage-Controllable Flexible-Pass-Gates
Fabrication of a Vertical-Channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor Using a Neutral Beam Etching
Investigation of N-Channel Triple-Gate MOSFETs on (100) SOI Substrate
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology
Dual-Metal-Gate Transistors with Symmetrical Threshold Voltages Using Work-Function-Tuned Ta/Mo Bilayer Metal Gates
Ta/Mo Stack Dual Metal Gate Technology Applicable to Gate-First Processes
P-Channel Vertical Double-Gate MOSFET Fabricated by Utilizing Ion-Bombardment-Retarded Etching Processs
Atomic Layer Deposition of SiO
Atomic Layer Deposition of SiO₂ for the Performance Enhancement of Fin Field Effect Transistors

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