MASAHARA Meishoku | Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology

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著作論文

A Novel Process for Fabrication of Gated Silicon Field Emitter Array Taking Advantage of Ion Bombardment Retarded Etching
Enhancing Noise Margins of Fin-Type Field Effect Transistor Static Random Access Memory Cell by Using Threshold Voltage-Controllable Flexible-Pass-Gates
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction
Fabrication of ultrathin Si Channel Wall For Vertical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG MOSFET) by Using Ion-Bombardment-Retarded Etching (IBRE)
Demonstration of Dopant Profiling in Ultrathin Channels of Vertical-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect-Transistor by Scanning Nonlinear Dielectric Microscopy
Device Design Consideration for V_-Controllable Four-Terminal Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor
P-Channel Vertical Double-Gate MOSFET Fabricated by Utilizing Ion-Bombardment-Retarded Etching Processs
Novel Process for Vertical Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) Fabrication
Programmable Conductivity of Silicon Nanowires with Side Gates by Surface Charging

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