Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)

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概要

• 論文の詳細を見る

• Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.

• 社団法人電子情報通信学会の論文
• 2001-12-01

著者

• YAMAGUCHI Yasuo

  Institute for Materials Research, Tohoku University

• Yamaguchi Y

  Tohoku Univ. Sendai

• Yamaguchi Y

  Kumamoto Techno Res. Park Kumamoto Jpn

• YAMAGUCHI Yasuo

  the ULSI Development Center, Mitsubishi Electric Corporation

• IPPOSHI Takashi

  the ULSI Development Center, Mitsubishi Electric Corporation

• UEDA Kimio

  the ULSI Development Center, Mitsubishi Electric Corporation

• MASHIKO Koichiro

  the ULSI Development Center, Mitsubishi Electric Corporation

• MAEGAWA Shigeto

  the ULSI Development Center, Mitsubishi Electric Corporation

• INUISHI Masahide

  the ULSI Development Center, Mitsubishi Electric Corporation

• NISHIMURA Tadashi

  the ULSI Development Center, Mitsubishi Electric Corporation

• IPPOSHI Takashi

  Advanced Device Development Dept., Renesas Technology Corp.

• INUISHI Masahide

  Advanced Device Development Dept., Renesas Technology Corp.

• Ueda K

  Mitsubishi Electric Corp. Itami‐shi Jpn

• Ueda Kimio

  System Lsi Development Center Mitsubishi Electric Corp.

• Maegawa Shigeto

  Advanced Device Development Dept. Renesas Technology Corp.

• Yamaguchi Y

  Central Workshop Osaka University

• Ueda K

  System Lsi Laboratory Mitsubishi Electric Corporation

• Ipposhi Takashi

  Advanced Device Development Dept. Renesas Technology Corp.

• Mashiko Koichiro

  The Ulsi Development Center Mitsubishi Electric Corporation

• Mashiko Koichiro

  System Lsi Development Center Mitsubishi Electric Corporation

• Mashiko Koichiro

  System Lsi Laboratory Mitsubishi Electric Corporation

• Nishimura Tadashi

  The Ulsi Development Center Mitsubishi Electric Corporation

• Nishimura Tadashi

  Ulsi Research And Development Center Mitsubishi Electric Corporation

• Yamaguchi Yasuo

  The Ulsi Development Center Mitsubishi Electric Corporation

• Ueda K

  Ntt Atsugi‐shi Jpn

• Ueda Katsuhiko

  Department Of Information Engineering Nara National College Of Technology

• Ipposhi T

  Advanced Device Development Dept. Renesas Technology Corp.

• Inuishi Masahide

  Advanced Device Development Dept. Renesas Technology Corp.

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