Ueda K | Ntt Atsugi‐shi Jpn

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概要

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著作論文

Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure
A Study on Semi-Blind Adaptive equalizer for PSK and QPSK Signals
A Missense Mutation in Tomato mosaic virus L_A-Fukushima Genome Determines Its Symptomless Systemic Infection of Tomato
Discrimination between Virulent and Attenuated Isolates of Tomato mosaic virus by Restriction Fragment Length Polymorphism
Blind Adaptive Equalizer Based on CMA and LMS Algorithm(Fundamental Theories)
Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits (Special Issue on Low-power LSIs and Technologies)
SOI/CMOS Circuit Design for High-Speed Communication LSIs (Special Issue on New Concept Device and Novel Architecture LSIs)
An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital Signal Processor
A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption
3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
A New Emitter-Follower Circuit for High-Speed and Low-Power ECL
Automatic Seal Imprint Verification System with Imprint Quality Assessment Function and Its Performance Evaluation

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