IPPOSHI Takashi | ULSI Development Center, Mitsubishi Electric Corporation

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著作論文

A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
Suppression of Parasitic MOSFETs at LOCOS Edge Region in Partially Depleted SOI MOSFETs
Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
Impact of μA-ON-Current Gate-All-Around TFT (GAT) for Static RAM of 16Mb and beyond
Impact of μ A-ON-Current Gate All-Around TFT (GAT) for 16MSRAM and Beyond
A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

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