Maegawa Shigeto | Advanced Device Development Dept. Renesas Technology Corp.

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概要

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著作論文

Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation
The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
Suppression of Self-Heating in Hybrid Trench Isolated SOI MOSFETs with Poly-Si plug and W plug
Impact of μA-ON-Current Gate-All-Around TFT (GAT) for Static RAM of 16Mb and beyond
Impact of μ A-ON-Current Gate All-Around TFT (GAT) for 16MSRAM and Beyond
Impact of Body Bias Controlling in Partially Depleted SOI Devices with Hybrid Trench Isolation Technology
A 90nm-node SOI Technology for RF Applications
SOI/CMOS Circuit Design for High-Speed Communication LSIs (Special Issue on New Concept Device and Novel Architecture LSIs)
A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

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