Iwamatsu Toshiaki | Advanced Device Development Dept. Renesas Technology Corp.

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概要

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著作論文

Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation
The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
Suppression of Parasitic MOSFETs at LOCOS Edge Region in Partially Depleted SOI MOSFETs
Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Suppression of Self-Heating in Hybrid Trench Isolated SOI MOSFETs with Poly-Si plug and W plug
Impact of Body Bias Controlling in Partially Depleted SOI Devices with Hybrid Trench Isolation Technology
A 90nm-node SOI Technology for RF Applications
Direct Measurement of Transient Drain Currents in Partially-depleted SOI NMOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
A Robust Silicon-on-Insulator Static-Random-Access-Memory Architecture by using Advanced Actively Body-Bias Controlled Technology
Electrical Characteristics and Crystal Quality Analysis of Thin-Body $\langle 100\rangle$ Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Using Two-Step Elevated Silicon Epitaxial Process

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