IPPOSHI Takashi | Advanced Device Development Dept., Renesas Technology Corp.

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概要

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著作論文

Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
Suppression of Parasitic MOSFETs at LOCOS Edge Region in Partially Depleted SOI MOSFETs
Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
Suppression of Self-Heating in Hybrid Trench Isolated SOI MOSFETs with Poly-Si plug and W plug
Impact of μ A-ON-Current Gate All-Around TFT (GAT) for 16MSRAM and Beyond
Magnetic Quantum Oscillations Due to Auger Recombination and Shockley-Read Recombination Processes in n-Hg_Cd_xTe
Impact of Body Bias Controlling in Partially Depleted SOI Devices with Hybrid Trench Isolation Technology
A 90nm-node SOI Technology for RF Applications
A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

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