Mashiko Koichiro | System Lsi Laboratory Mitsubishi Electric Corporation

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概要

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著作論文

Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits (Special Issue on Low-power LSIs and Technologies)
SOI/CMOS Circuit Design for High-Speed Communication LSIs (Special Issue on New Concept Device and Novel Architecture LSIs)
3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
A New Emitter-Follower Circuit for High-Speed and Low-Power ECL

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