Makino H | Mitsubishi Electric Corp. Itami‐shi Jpn

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著作論文

Novel VLIW Code Compaction Method for a 3D Geometry Processor
A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(Low-Power System LSI, IP and Related Technologies)
Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)
A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation(the IEEE International Conference on SISPAD '02)
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology

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