A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(<Special Section>Low-Power System LSI, IP and Related Technologies)
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概要
- 論文の詳細を見る
We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 μm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0V.
- 社団法人電子情報通信学会の論文
- 2004-04-01
著者
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Notani H
System Lsi Laboratory Mitsubishi Electric Corporation
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Notani Hiromi
Renesas Technology
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Notani Hiromi
Renesas Technol. Corp.
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Notani Hiromi
Lsi Laboratory Mitsubishi Electric Corporation
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Shibagaki Takeshi
Renesas Technology
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Notani H
Renesas Technology
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Makino Hiroshi
Renesas Technology Corporation
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SHIMADA Takahiro
Renesas Technology
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NAKASE Yasunobu
Renesas Technology
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IWADE Shuhei
Osaka Institute of Technology
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Nakase Yasunobu
The System Lsi Laboratory Mitsubishi Electric Corporation
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Makino H
Mitsubishi Electric Corp. Itami‐shi Jpn
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NAKASE Yasunobu
Renesas Electronics Corp.
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