招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)

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概要

• 論文の詳細を見る

• We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair scheme for an embedded 6T-SRAM to achieve a KGD-SoC. We febricated a 16M-SRAM with these techniques using 65 nm LSTP technology, and confirmed its efficient operation. The WLBI mode has almost no area penalyy and a speed penalty of only 50 ps. The leak-bit redundancy area penalty is less than 2%.

• 2007-04-05

著者

• Nii Koji

  Renesas Electronics Corporation

• Nii Koji

  Renesas Technology Corporation

• Nii K

  Renesas Technol. Corp. Itami‐shi Jpn

• Makino Hiroshi

  Renesas Technology Corporation

• SHINOHARA Hirofumi

  Renesas Technology Corporation

• Makino H

  Mitsubishi Electric Corp. Itami‐shi Jpn

• Arakawa Masashi

  Renesas Technology Corporation

• Uchida Takahiro

  Renesas Technology Corporation

• Imaoka Susumu

  Renesas Design Corporation

• Ohbayashi Shigeki

  Renesas Technology Corporation

• Yabuuchi Makoto

  Renesas Technology Corporation

• Kono Kazushi

  Renesas Technology Corporation

• Oda Yuji

  Shikino High-Tech Corporation

• Usui Keiichi

  Daioh Electric Co. Ltd.

• Yonezu Toshiaki

  Renesas Technology Corporation

• Iwamoto Takeshi

  Renesas Technology Corporation

• Tsukamoto Yasumasa

  Renesas Technology Corporation

• Ishibashi Koichiro

  Renesas Technology Corporation

• Ishibashi Koichiro

  Renesas Technology

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