Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(<特集>Special Issue on High-Performance and Low-Power Microprocessors)
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概要
- 論文の詳細を見る
An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block.
- 社団法人電子情報通信学会の論文
- 2002-02-01
著者
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HARADA Ayako
Faculty of Pharmaceutical Sciences, Teikyo University
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Wada Tetsuro
System Lsi Development Center Mitsubishi Electric Corporation
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Matsuda Yoshio
System Lsi Laboratory Mitsubishi Electric Corporation
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Yoshimoto Masahiko
Mitsubishi Electric Corporation
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IWADE Shuhei
Osaka Institute of Technology
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TAKATA Hidehiro
System LSI Development Center,Mitsubishi Electric Corporation
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AKIYAMA Rei
Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation
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YAMANAKA Tadao
Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation
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OHKUMA Haruyuki
Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation
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SUETSUGU Yasue
Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation
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KANAOKA Toshihiro
Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation
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KUMAKI Satoshi
System LSI Development Center,Mitsubishi Electric Corporation
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ISHIHARA Kazuya
System LSI Development Center,Mitsubishi Electric Corporation
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HANAMI Atsuo
System LSI Development Center,Mitsubishi Electric Corporation
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MATSUMURA Tetsuya
System LSI Development Center,Mitsubishi Electric Corporation
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WATANABE Tetsuya
System LSI Development Center,Mitsubishi Electric Corporation
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AJIOKA Yoshihide
System LSI Division, Mitsubishi Electric Corporation
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IWADE Syuhei
System LSI Development Center,Mitsubishi Electric Corporation
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Harada Ayako
Reproductive Pediatric And Infectious Science Yamaguchi University School Of Medicine
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Harada Ayako
Faculty Of Pharmaceutical Sciences Teikyo University
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Harada Ayako
Information Technology R&d Center Mitsubishi Electric Corporation
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Harada Ayako
Department Of Molecular Biodynamics The Tokyo Metropolitan Institute Of Medical Science (rinshoken)
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Yamanaka Toshio
The Graduate School Of Advanced Sciences Of Matter Hiroshima University:texas Instruments Japan Limi
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TAKATA Hidehiro
Renesas Technology
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AKIYAMA Rei
Renesas Device Design
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YASUDA Shutarou
Renesas Device Design
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Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
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Hanami Atsuo
System Lsi Development Center Mitsubishi Electric Corporation
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Kumaki Satoshi
System Lsi Development Center Mitsubishi Electric Corporation
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Yamanaka T
Renesas Device Design
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Ishihara Kazuya
System Lsi Development Center Mitsubishi Electric Corporation
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Yoshimoto M
Department Of Computer Science And Systems Engineering Kobe University
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Takata Hidehiro
System Lsi Development Center Mitsubishi Electric Corporation
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Ajioka Yoshihide
System Lsi Division Mitsubishi Electric Corporation
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Matsumura T
System Lsi Development Center Mitsubishi Electric Corporation
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Ohkuma Haruyuki
Electronic Devices Design Center Mitsubishi Electric Engineering Corporation
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Watanabe T
Microsystem Integration Laboratories Ntt Corporation
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Kanaoka Toshihiro
Electronic Devices Design Center Mitsubishi Electric Engineering Corporation
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Matsuda Yoshio
System Lsi Development Center Mitsubishi Electric Corporation
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