A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
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概要
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This paper describes the design of a high-speed 4-2 compressor for fast multipliers. Through the survey of the six kinds of representative conventional 4-2 compressor (RBA1-3 and NBA1-3) in both the redundant binary (RB) and the normal binary (NB) scheme, we extracted two problems that degrades the operating speed. The first is the use of multi-input complex gates and the second is the existence of transmission gates (TG) at the input and/or output stages. To solve these problems, we propose high-speed 4-2 compressors using the RB scheme, which we call the high-speed redundant binary adders (HSRBAs). Six kinds of HSRBAs, HSRBA1-6, were derived by making the Boolean equations suitable for high-speed CMOS circuits. Among them, HSRBA2, HSRBA4 and HSRBA6 have no multi-input complex gate and input/output TG, and perform at a delay time of 0.89 ns which is the fastest of all 4-2 compressors. We investigated the logical relation between HSRBAs and conventional 4-2 compressors by analyzing the Boolean equations for each circuit. This investigation shows that all the conventional redundant binary adders RBA1-3 have the same logic structures as HSRBA2. We also showed the conventional normal binary adders NBA1-3 have the same logic structures as HSRBA1, HSRBA3 and HSRBA5, respectively. This implies all 4-2 compressors can be derived from the same equation regardless of RB or NB. We applied the HSRBA2 to a 54×54-bit multiplier using 0.5-μm CMOS technology. The multiplication time at the supply voltage of 3.3 V was 8.8 ns. This is the fastest 54×54-bit multiplier with 0.5-μm CMOS so far, and 83% of the speed improvement is due to the high speed 4-2 compressor.
- 1996-04-25
著者
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MASHIKO Koichiro
System LSI Development Center, Mitsubishi Electric Corporation
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HORIBA Yasutaka
System LSI Development Center, Mitsubishi Electric Corporation
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Horino Y
Advanced Device Development Dept. Renesas Technology Corp.
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Makino Hiroshi
Renesas Technology Corporation
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SUZUKI Hiroaki
System LSI Development Center, Mitsubishi Electric Corporation
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MAKINO Hiroshi
System LSI Development Center, Mitsubishi Electric Corporation
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NAKASE Yasunobu
Renesas Technology
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HORIBA Yasutaka
The authors are with Kita-Itami Works, Mitsubishi Electric Corporation
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Nakase Yasunobu
The System Lsi Laboratory Mitsubishi Electric Corporation
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Nakase Yasunobu
System Lsi Development Center Mitsubishi Electric Corporation
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Makino H
Mitsubishi Electric Corp. Itami‐shi Jpn
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SUMI Tadashi
the System LSI Laboratory, Mitsubishi Electric Corporation
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MORINAKA Hiroyuki
System LSI Laboratory, Mitsubishi Electric Corporation
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SHINOHARA Hirofumi
Headquarters, Mitsubishi Electric Corporation
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SUMI Tadashi
System LSI Laboratory, Mitsubishi Electric Corporation
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Horiba Yasutaka
Lsi Laboratory Mitsubishi Electric Corporation
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Horiba Yasutaka
The Authors Are With Kita-itami Works Mitsubishi Electric Corporation
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Horiba Yasutaka
System Lsi Laboratory Mitsubishi Electric Corporation
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Mashiko Koichiro
The Ulsi Development Center Mitsubishi Electric Corporation
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Mashiko Koichiro
System Lsi Development Center Mitsubishi Electric Corporation
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Mashiko Koichiro
System Lsi Laboratory Mitsubishi Electric Corporation
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Shinohara Hirofumi
Headquarters Mitsubishi Electric Corporation
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Suzuki H
Ntt Photonics Labs. Ntt Corporation
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Sumi T
The Authors Are With Electronics Research Laboratory Matsushita Electronics Corporation
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Sumi T
Department Of Obstetrics And Gynecology Osaka City University Medical School
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Suzuki H
Hiroshima Univ. Higashi‐hiroshima‐shi Jpn
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Suzuki Hiroaki
System Lsi Development Center Mitsubishi Electric Co.
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