A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
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概要
- 論文の詳細を見る
We present a 64-b adder having a 2.6-ns delay time at 3.3 V power supply within 0.27 mm^2 using 0.5-μm CMOS technology. We derived our adder design from architectural level considerations. The considerations include not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. As a result, a 64-b adder, (56-b Carry Look-ahead Adder (CLA) +8-b Carry Select Adder (CSA)), was designed. In this design, a new carry select scheme called Modified Carry Select (MCS) is also proposed.
- 社団法人電子情報通信学会の論文
- 1996-04-25
著者
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MASHIKO Koichiro
System LSI Development Center, Mitsubishi Electric Corporation
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Makino Hiroshi
Renesas Technology Corporation
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SUZUKI Hiroaki
System LSI Development Center, Mitsubishi Electric Corporation
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MAKINO Hiroshi
System LSI Development Center, Mitsubishi Electric Corporation
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NAKASE Yasunobu
Renesas Technology
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Nakase Yasunobu
The System Lsi Laboratory Mitsubishi Electric Corporation
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Nakase Yasunobu
System Lsi Development Center Mitsubishi Electric Corporation
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Makino H
Mitsubishi Electric Corp. Itami‐shi Jpn
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SUMI Tadashi
the System LSI Laboratory, Mitsubishi Electric Corporation
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MORINAKA Hiroyuki
System LSI Laboratory, Mitsubishi Electric Corporation
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SUMI Tadashi
System LSI Laboratory, Mitsubishi Electric Corporation
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Mashiko Koichiro
The Ulsi Development Center Mitsubishi Electric Corporation
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Mashiko Koichiro
System Lsi Development Center Mitsubishi Electric Corporation
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Mashiko Koichiro
System Lsi Laboratory Mitsubishi Electric Corporation
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Suzuki H
Ntt Photonics Labs. Ntt Corporation
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Sumi T
The Authors Are With Electronics Research Laboratory Matsushita Electronics Corporation
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Sumi T
Department Of Obstetrics And Gynecology Osaka City University Medical School
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Suzuki H
Hiroshima Univ. Higashi‐hiroshima‐shi Jpn
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Suzuki Hiroaki
System Lsi Development Center Mitsubishi Electric Co.
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