3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
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概要
- 論文の詳細を見る
This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8μm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so fan above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).
- 社団法人電子情報通信学会の論文
- 1995-07-25
著者
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SATO Hisayasu
System LSI Development Center, Mitsubishi Electric Corporation
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UEDA Kimio
System LSI Development Center, Mitsubishi Electric Corporation
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SASAKI Nagisa
System LSI Division, Mitsubishi Electric Corporation
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Sato H
Riken
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Ueda K
Mitsubishi Electric Corp. Itami‐shi Jpn
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Ueda Kimio
System Lsi Development Center Mitsubishi Electric Corp.
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Saito H
Information Technology R Amp D Center Mitsubishi Electric Corporation
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Ueda K
System Lsi Laboratory Mitsubishi Electric Corporation
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Mashiko Koichiro
The Ulsi Development Center Mitsubishi Electric Corporation
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Mashiko Koichiro
System Lsi Development Center Mitsubishi Electric Corporation
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Mashiko Koichiro
System Lsi Laboratory Mitsubishi Electric Corporation
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KUBO Shunji
ULSI Laboratory, Mitsubishi Electrio Corp.
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Ueda K
Ntt Atsugi‐shi Jpn
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Masahiko Koichiro
System LSI Laboratory, Mitsubishi Electric Corporation
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Sasaki Nagisa
System Lsi Division Mitsubishi Electric Corporation
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Ueda Katsuhiko
Department Of Information Engineering Nara National College Of Technology
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Kubo Shunji
Ulsi Laboratory Mitsubishi Electric Corporation
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Shibata H
System Lsi Development Center Mitsubishi Electric Corporation
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