Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits (Special Issue on Low-power LSIs and Technologies)

スポンサーリンク

概要

• 論文の詳細を見る

• Based on the partially-depleted, thin-film SOI/CMOS technology, the influence of reduced junction capacitance on the performance of the elementary gates and large scale gate array chip is reviewed. To further reduce the power consumption, SOI-specific device configurations, in which the body-bias is individually controlled, are effective in lowering the supply voltage and hence the power consumption while keeping the circuit speed. Two attempts are introduced: (1) DTMOS (Dynamic-Threshold MOS)/SOI to achieve ultra low-voltage and yet high-speed operation, and (2) ABB (Active-Body-Bias) MOS to enhance the current drive under the low supply voltage.

• 社団法人電子情報通信学会の論文
• 2000-11-25

著者

• UEDA Kimio

  System LSI Development Center, Mitsubishi Electric Corporation

• WADA Yoshiki

  System LSI Development Center, Mitsubishi Electric Corporation

• MASHIKO Koichiro

  System LSI Development Center, Mitsubishi Electric Corporation

• Ueda K

  Mitsubishi Electric Corp. Itami‐shi Jpn

• Ueda Kimio

  System Lsi Development Center Mitsubishi Electric Corp.

• Wada Yoshiki

  System Lsi Development Center Mitsubishi Electric Corp.

• Wada Y

  Advanced Technology R&d Center Mitsubishi Electric Corporation

• KUBO Kazuo

  Information Technology R amp D Center, Mitsubishi Electric Corporation

• Ueda K

  System Lsi Laboratory Mitsubishi Electric Corporation

• Mashiko Koichiro

  The Ulsi Development Center Mitsubishi Electric Corporation

• Mashiko Koichiro

  System Lsi Development Center Mitsubishi Electric Corporation

• Mashiko Koichiro

  System Lsi Laboratory Mitsubishi Electric Corporation

• Ueda K

  Ntt Atsugi‐shi Jpn

• YOSHOMURA Tsutomu

  System LSI Development Center, Mitsubishi Electric Corp.

• HIROTA Takanori

  the System LSI Division, Mitsubishi Electric Corp.

• TAKASOH Jun

  High Frequency & Optical Semiconductor Division, Mitsubishi Electric Corp.

• Kubo Kazuo

  Information Technology R&d Center Mitsubishi Electric Corp.

• Takasoh J

  Mitsubishi Electric Corp. Itami‐shi Jpn

• Ueda Katsuhiko

  Department Of Information Engineering Nara National College Of Technology

• Yoshimura T

  Mitsubishi Electric Corp. Itami‐shi Jpn

関連論文

• Hysteretic Josephson Junction Behavior of Ba_K_xBiO_3 Grain Boundary Junctions Using SrTiO_3 Bicrystal Substrates
• Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
• A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
• A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
• Analysis of the Delay Distributions of 0.5μm SOI LSIs (Special Issue on SOI Devices and Their Process Technologies)
• High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure
• A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
• GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer Chip Sets (Special Issue on Ultra-High-Speed LSIs)
• A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
• A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
• A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
• A Study on Semi-Blind Adaptive equalizer for PSK and QPSK Signals
• A Missense Mutation in Tomato mosaic virus L_A-Fukushima Genome Determines Its Symptomless Systemic Infection of Tomato
• Discrimination between Virulent and Attenuated Isolates of Tomato mosaic virus by Restriction Fragment Length Polymorphism
• Blind Adaptive Equalizer Based on CMA and LMS Algorithm(Fundamental Theories)
• Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits (Special Issue on Low-power LSIs and Technologies)
• SOI/CMOS Circuit Design for High-Speed Communication LSIs (Special Issue on New Concept Device and Novel Architecture LSIs)
• An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital Signal Processor
• A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption
• 3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
• A New Emitter-Follower Circuit for High-Speed and Low-Power ECL
• Aiming for SIS Mixers Using Ba_<1-x>K_xBiO_3 Bicrystal Junctions (Special Issue on Basic Properties and Applications of Superconductive Electron Devices)
• Fabrication Of Full Hign-T_c Superconducting YBa_2Cu_3O Trilayer Junctions Using a Polishing Technique
• YBaCuO/PrBaCuO/YBaCuO Trilayer Junctions on Vicinal Substrates : Superconductors
• Improvement in Ba_K_xBiO_3 Grain Boundary Junctions by Ar^+ Beam Irradiation
• Significant Improvement in Ba_K_xBiO_3 Grain Boundary Junctions on MgO Bicrystal Substrates by Minimal BaBiO_3 Sputtering
• Automatic Seal Imprint Verification System with Imprint Quality Assessment Function and Its Performance Evaluation
• High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure

もっと見る 閉じる

スポンサーリンク