A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)

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概要

• 論文の詳細を見る

• This paper describes a 0.35 μm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35 μm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35 μm 3.3 V bulk-CMOS gate array.

• 社団法人電子情報通信学会の論文
• 2000-02-25

著者

• YAMAGUCHI Yasuo

  Institute for Materials Research, Tohoku University

• Yamaguchi Y

  Tohoku Univ. Sendai

• Yamaguchi Y

  Kumamoto Techno Res. Park Kumamoto Jpn

• IWAMATSU Toshiaki

  ULSI Laboratory, Mitsubishi Electric Corporation

• YAMAGUCHI Yasuo

  ULSI Laboratory, Mitsubishi Electric Corporation

• MAEGAWA Shigeto

  ULSI Laboratory, Mitsubishi Electric Corporation

• UEDA Kimio

  System LSI Development Center, Mitsubishi Electric Corporation

• MAEDA Shigenobu

  ULSI Development Center, Mitsubishi Electric Corporation

• NII Koji

  System LSI Development Center, Mitsubishi Electric Corporation

• WADA Yoshiki

  System LSI Development Center, Mitsubishi Electric Corporation

• IPPOSHI Takashi

  ULSI Development Center, Mitsubishi Electric Corporation

• MASHIKO Koichiro

  System LSI Development Center, Mitsubishi Electric Corporation

• HORIBA Yasutaka

  System LSI Development Center, Mitsubishi Electric Corporation

• Horino Y

  Advanced Device Development Dept. Renesas Technology Corp.

• IWAMATSU Toshiaki

  Advanced Device Development Dept., Renesas Technology Corp.

• IPPOSHI Takashi

  Advanced Device Development Dept., Renesas Technology Corp.

• Nii Koji

  Renesas Technology Corporation

• Nii K

  Renesas Technol. Corp. Itami‐shi Jpn

• Ueda K

  Mitsubishi Electric Corp. Itami‐shi Jpn

• Ueda Kimio

  System Lsi Development Center Mitsubishi Electric Corp.

• Wada Yoshiki

  System Lsi Development Center Mitsubishi Electric Corp.

• Wada Y

  Advanced Technology R&d Center Mitsubishi Electric Corporation

• Maegawa Shigeto

  Advanced Device Development Dept. Renesas Technology Corp.

• HORIBA Yasutaka

  The authors are with Kita-Itami Works, Mitsubishi Electric Corporation

• Yamaguchi Y

  Central Workshop Osaka University

• Ueda K

  System Lsi Laboratory Mitsubishi Electric Corporation

• Maegawa Shigeto

  Ulsi Development Center Mitsubishi Electric Corporation

• Horiba Yasutaka

  Lsi Laboratory Mitsubishi Electric Corporation

• Horiba Yasutaka

  The Authors Are With Kita-itami Works Mitsubishi Electric Corporation

• Horiba Yasutaka

  System Lsi Laboratory Mitsubishi Electric Corporation

• Maeda Shigenobu

  Ulsi Development Center Mitsubishi Electric Corporation

• Ipposhi Takashi

  Advanced Device Development Dept. Renesas Technology Corp.

• Mashiko Koichiro

  The Ulsi Development Center Mitsubishi Electric Corporation

• Mashiko Koichiro

  System Lsi Development Center Mitsubishi Electric Corporation

• Mashiko Koichiro

  System Lsi Laboratory Mitsubishi Electric Corporation

• Iwamatsu Toshiaki

  Advanced Device Development Dept. Renesas Technology Corp.

• Ueda K

  Ntt Atsugi‐shi Jpn

• Ueda Katsuhiko

  Department Of Information Engineering Nara National College Of Technology

• Ipposhi T

  Advanced Device Development Dept. Renesas Technology Corp.

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