A Programmable Geometry Processor with Enhanced Four-Parallel SIMD Type Processing Core for PC-Based 3D Graphics

概要

論文の詳細を見る
This paper describes a kind of 3D graphics geometry processor architecture for high performance/cost 3D graphics, its application to a real chip, and the results of performance evaluation. In order to establish the high speed geometry processing, dedicated hardware is introduced for accelerating special operations, such as power calculations, clip tests, and program address generation. The dedicated hardware consists of a modified floating-point multiplier in a four-parallel SIMD processing core, a clip test unit, and an internal program address generation scheme optimized to geometry processing mode. Special instructions corresponding to the dedicated schemes are also defined and added. The parallelism of the SIMD core is adjusted to a geometry data structure. Employing dedicated hardware and software significantly accelerates these complicated operations deriving from geometry algorithms. The collaboration of the hardware design and the software design considerably reduces instruction step counts for complex processing. Two kinds of program are dealt with in the proposed architecture. One is a special case program containing few conditional jump instructions, and the other is a general case program combining many program routines. The proposed program address generation scheme provides the automatic selection of a program optimized to each geometry processing mode. By this program address generation scheme and the program types, the frequency of the conditional jump operations, that usually disturb a pipeline operation, are minimized under practical use. Additionally, the programmable design and this program address generation scheme facilitate the load balancing of the geometry calculations with the CPU. A programmable geometry processor was fabricated by using 0.35μm CMOS process as an application of this architecture. One point three million transistors are integrated in a 11.84×12.07mm^2 die. The increase of the gate counts for all the dedicated hardware is a total of 24K gates and is approximately only a 7.4% increase of the total gate count. This chip operates at 150 MHz, and achieves the processing performance of 5.8M vertex/sec. The result shows that the proposed programmable architecture (ESIMD: Enhanced SIMD) is 2.3 times more cost effective than a programmable geometry LSI reported previously.
社団法人電子情報通信学会の論文
2002-05-01

A Programmable Geometry Processor with Enhanced Four-Parallel SIMD Type Processing Core for PC-Based 3D Graphics

スポンサーリンク

概要

著者

関連論文

スポンサーリンク