Static Linearity Error Analysis of Subranging A/D Converters (Special Section on Analog Technologies in Submicron Era)

概要

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An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f_s and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 1O-bit accuracy.
社団法人電子情報通信学会の論文
1996-02-25