A 10-bit 50 MS/s 300 mW A/D Converter Using Reference Feed-Forward Architecture (Special Issue on Low-Power and High-Speed LSI Technologies)

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This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecuture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5 μm CMOS technology, and it operates at 50 MS/s with a 300-mW (V_<dd>=3.0 V) power consumption. The differential linearity error of less than +/- 1 LSB is obtained.
社団法人電子情報通信学会の論文
1997-12-25