A 12bit Resolution 200 kFLIPS Fuzzy Inference Processor (Special Issue on New Architecture LSIs)

概要

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A fuzzy inference processor which performs fuzzy inference with 12-bit resolution input at 200 kFLIPS (Fuzzy Logical Inference Per Second) has been developed. To keep the cost performance, not parallel processing hardware but processor type hardware is employed. Dedicated membership function generators, rule instructions and modified add / divide algorithm are adopted to attain the performance. The membership function generators calculate a membership function value in less than a half clock cycle. Rule instructions calculate the grade of a rule by one instruction. Antecedent processing and consequent processing are pipelined by the modified add / divide algorithm. As a result, total inference time is significantly reduced. For example, in the case of typical inference (about 20 rules with 2 to 4 inputs and 1 output), the total inference needs approximately 100 clock cycles. Furthermore by adding a mechanism to calculate the variance and maximum grade of the final membership function, it is enabled to evaluate the inference reliability. The chip, fabricated by 1 μm CMOS technology, contains 86k transistors in a 7.5×6.7 mm die size. The chip operates at more than 20 MHz clock frequency at 5V.
社団法人電子情報通信学会の論文
1993-07-25