A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder(Special Issue on Multimedia, Network, and DRAM LSIs)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper describes a chip set architecture and its implementation for programmable MPEG2 MP@ML (main profile at main level) video encoder. The chip set features a functional partitioning architecture based on the MPEG2 layer structure. Using this partitioning scheme, an optimized system configuration with double bus structure is proposed. In addition, a hybrid architecture with dual video-oriented on-chip RISC processors and dedicated hardware and a hierarchical pipeline scheme covering all layers are newly introduced to realize flexibility. Also, effective motion estimation is achieved by a scalable solution for high picture quality. Adopting these features, three kinds of VLSI have been development using 0.5 micron double metal CMOS technology. The chip set consists of a controller-LSI (C-LSI), a macroblock level pixel processor-LSI (P-LSI) and a motion estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports all the layer processing including rate-control and realizes real-time encoding for ITU-R-601 resolution video (720×480 pixels at 30 frames/s) with glue less logic. The exhaustive motion estimation capability is scalable up to ±63.5 and ±15.5 in the horizontal and vertical directions respectively. This chip set solution realizes a low cost MPEG2 video encoder system with excellent video quality on a single PC extension board. The evaluation system and application development environment is also introduced.

• 社団法人電子情報通信学会の論文
• 1998-05-25

著者

• HARADA Ayako

  Faculty of Pharmaceutical Sciences, Teikyo University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• KUMAKI Satoshi

  System LSI Development Center,Mitsubishi Electric Corporation

• ISHIHARA Kazuya

  System LSI Development Center,Mitsubishi Electric Corporation

• MATSUMURA Tetsuya

  System LSI Development Center,Mitsubishi Electric Corporation

• AJIOKA Yoshihide

  System LSI Division, Mitsubishi Electric Corporation

• Harada Ayako

  Reproductive Pediatric And Infectious Science Yamaguchi University School Of Medicine

• Harada Ayako

  Faculty Of Pharmaceutical Sciences Teikyo University

• Harada Ayako

  Information Technology R&d Center Mitsubishi Electric Corporation

• Harada Ayako

  Department Of Molecular Biodynamics The Tokyo Metropolitan Institute Of Medical Science (rinshoken)

• SUMI Tadashi

  the System LSI Laboratory, Mitsubishi Electric Corporation

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Nakagawa S

  Omron Corp. Information Technol. Res. Center Kyoto‐shi Jpn

• Hanami Atsuo

  System Lsi Development Center Mitsubishi Electric Corporation

• Sumi Tadashi

  The System Lsi Development Center Mitsubishi Electric Corporation

• Kumaki Satoshi

  System Lsi Development Center Mitsubishi Electric Corporation

• Segawa Hiroshi

  The Authors Are With System Lsi Development Center Mitsubishi Electric Corporation

• Ishihara Kazuya

  System Lsi Development Center Mitsubishi Electric Corporation

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• KASEZAWA Tadashi

  the Information Technology R&D Center, Mitsubishi Electric Corporation

• MATSUMURA Tetsuya

  the System LSI Development Center, Mitsubishi Electric Corporation

• KUMAKI Satoshi

  the System LSI Development Center, Mitsubishi Electric Corporation

• ISHIHARA Kazuya

  the System LSI Development Center, Mitsubishi Electric Corporation

• SEGAWA Hiroshi

  the System LSI Development Center, Mitsubishi Electric Corporation

• HANAMI Atsuo

  the System LSI Development Center, Mitsubishi Electric Corporation

• MATSUURA Yoshinori

  the System LSI Development Center, Mitsubishi Electric Corporation

• NAKAGAWA Shin-ichi

  the System LSI Division, Mitsubishi Electric Corporation

• AJIOKA Yoshihide

  the Manufacturing Technology Division, Mitsubishi Electric Corporation

• MAEDA Atsuhi

  ULSI Laboratory, Mitsubishi Electric Corporation

• YOSHIMOTO Masahiko

  the System LSI Division, Mitsubishi Electric Corporation

• Kasezawa Tadashi

  The Information Technology R&d Center Mitsubishi Electric Corporation

• Maeda Atsuhi

  Ulsi Laboratory Mitsubishi Electric Corporation

• Sato H

  Ntt Microsystem Integration Laboratories

• Ajioka Yoshihide

  System Lsi Division Mitsubishi Electric Corporation

• Matsumura T

  System Lsi Development Center Mitsubishi Electric Corporation

• Nakagawa S

  Communications Res. Lab. Koganei‐shi Jpn

関連論文

• Expression of a Novel 90-kDa Protein, Lsd90, Involved in the Metabolism of Very Long-chain Fatty Acid-containing Phospholipids in a Mitosis-defective Fission Yeast Mutant
• An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
• A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
• Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
• An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
• A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
• VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding(Low-Power System LSI, IP and Related Technologies)
• A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU(Low-Power System LSI, IP and Related Technologies)
• Red Blood Cells Highly Express Type I Platelet-Activating Factor-Acetylhydrolase (PAF-AH) Which Consists of the α_1/α_2 Complex
• Regulation of Activities of Cytidine 5'-Diphospho-Choline : 1-O-Alkyl-2-Acetyl-sn-Glycerol Cholinephosphotransferase, an Enzyme Responsible for de novo Synthesis of Platelet-Activating Factor, by Membrane Phospholipids
• Pineal Gland (Melatonin) Affects the Parturition Time, but not Luteal Function and Fetal Growth, in Pregnant Rats
• Changes in Telomerase Activity in Experimentally Induced Atretic Follicles of Immature Rats
• Role of transient hyperprolactinemia in the late follicular phase of the gonadotropin-stimulated cycle
• Alterations in Nitrate/Nitrite and Nitric Oxide Synthase in Preovulatory Follicles in Gonadotropin-Primed Immature Rat
• An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
• Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
• Ferroelectric Memory Circuit Technology and the Application to Contactless IC Card(Special Issue on Advanced Memory Devices Using High-ε and Ferroelectric Films)
• A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
• A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
• A Monoclonal Antibody, 3A10, Recognizes a Specific Amino Acid Sequence Present on a Series of Developmentally Expressed Brain Proteins
• A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
• VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
• A Dependable SRAM with 7T/14T Memory Cells
• A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
• Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
• Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
• An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
• A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
• A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
• Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
• A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
• Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
• Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
• A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
• 2 V/12O ns Embedded Flash EEPROM Circuit Technology (Special Issue on ULSI Memory Technology)
• A Highly Parallel DSP Architecture for Image Recognition
• A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
• A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
• A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
• A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
• A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
• A Variational Approach to Understanding the Ground State of a Square-Lattice Heisenberg Antiferromagnet
• Addendum to the Paper on UDRVB in One-Dimensional Spin-1/2 Heisenberg Systems with Frustration
• Exact Solution of the Ground State for Uniformly Distributed RVB in One-Dimensional Spen-1/2 Heisenberg Systems with Frustration
• Studies on the effects of initial injection doses of follicle stimulating hormone on the pregnancy and the ovarian hyperstimulation syndrome incidence in polycystic ovarian syndrome patients
• A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video (Special Issue on Multimedia, Analog and Processing LSIs)
• Nanometer-Scale Lithography on the Oligosilane Langmuir-Blodgett Film
• Photochemical Polymerization of Oligothiophenes
• Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE802.11e WLANs(Network)
• Static Linearity Error Analysis of Subranging A/D Converters (Special Section on Analog Technologies in Submicron Era)
• Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
• Future Technological and Economic Prospects for VLSI (Special Issue on LSI Memories)
• A 350-MS/s 3.3-V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
• A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor(Special Issue on Novel VLSI Processor Architectures)
• Image-Based Photorealistic 3D Reconstruction Using Hexagonal Representation(Computer Graphics)
• A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
• An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set(Special Section on Digital Signal Processing)
• A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder(Special Issue on Multimedia, Network, and DRAM LSIs)
• ULSI Realization of MPEG2 Realtime Video Encoder and Decoder : An Overview
• Synthesis and Photochemical Properties of the Orthogonal Porphyrin Triad Composed of Free-Base and Phosphorus(V) Porphyrins
• A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
• Reliable Sexing of Human Preimplantation Embryos : Analysis by DNA Amplification and Fluorescence in situ Hybridization
• A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
• Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
• A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
• 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
• A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

もっと見る 閉じる

スポンサーリンク