A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
スポンサーリンク
概要
- 論文の詳細を見る
A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed ransport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hard-wired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormons compntational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2mm x 14.2mm die with 11 million transistors.
- 2001-01-01
著者
-
HARADA Ayako
Faculty of Pharmaceutical Sciences, Teikyo University
-
Wada Tetsuro
System Lsi Development Center Mitsubishi Electric Corporation
-
Horino Y
Advanced Device Development Dept. Renesas Technology Corp.
-
Asano Ken-ichi
The Authors Are With Information Technology R&d Center Mitsubishi Electric Corporation
-
Yoshimoto Masahiko
Mitsubishi Electric Corporation
-
YAMADA Akira
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
TAKATA Hidehiro
The authors are with Electric Devices Design Center, Mitsubishi Electric Engineering Corporation
-
KUMAKI Satoshi
System LSI Development Center,Mitsubishi Electric Corporation
-
ISHIHARA Kazuya
System LSI Development Center,Mitsubishi Electric Corporation
-
MATSUMURA Tetsuya
System LSI Development Center,Mitsubishi Electric Corporation
-
MATSUMURA Tetsuya
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
KUMAKI Satoshi
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
SEGAWA Hiroshi
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
ISHIHARA Kazuya
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
HANAMI Atsuo
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
MATSUURA Yoshinori
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
SCOTZNIOVSKY Stefan
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
MURAYAMA Shu
The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation
-
WADA Tetsuro
The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation
-
OHIRA Hideo
The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation
-
SHIMADA Toshiaki
The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation
-
YOSHIDA Toyohiko
The authors are with System LSI Development Center, Mitsubishi Electric Corporation
-
YOSHIMOTO Masahiko
The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation
-
TSUCHIHASHI Koji
The authors are with Kita-Itami Works, Mitsubishi Electric Corporation
-
HORIBA Yasutaka
The authors are with Kita-Itami Works, Mitsubishi Electric Corporation
-
Harada Ayako
Reproductive Pediatric And Infectious Science Yamaguchi University School Of Medicine
-
Harada Ayako
Faculty Of Pharmaceutical Sciences Teikyo University
-
Harada Ayako
Information Technology R&d Center Mitsubishi Electric Corporation
-
Harada Ayako
Department Of Molecular Biodynamics The Tokyo Metropolitan Institute Of Medical Science (rinshoken)
-
Horiba Yasutaka
Lsi Laboratory Mitsubishi Electric Corporation
-
Horiba Yasutaka
The Authors Are With Kita-itami Works Mitsubishi Electric Corporation
-
Horiba Yasutaka
System Lsi Laboratory Mitsubishi Electric Corporation
-
TAKATA Hidehiro
Renesas Technology
-
Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
-
Scotzniovsky Stefan
The Authors Are With System Lsi Development Center Mitsubishi Electric Corporation
-
Yoshida Takeshi
Graduate School Of Advanced Sciences Of Matter Hiroshima University
-
Yoshida T
Graduate School Of Advanced Sciences Of Matter Hiroshima University
-
Ohira Hideo
The Authors Are With Information Technology R&d Center Mitsubishi Electric Corporation
-
Hanami Atsuo
System Lsi Development Center Mitsubishi Electric Corporation
-
Murayama Shu
The Authors Are With Information Technology R&d Center Mitsubishi Electric Corporation
-
Kumaki Satoshi
System Lsi Development Center Mitsubishi Electric Corporation
-
Segawa Hiroshi
The Authors Are With System Lsi Development Center Mitsubishi Electric Corporation
-
Ishihara Kazuya
System Lsi Development Center Mitsubishi Electric Corporation
-
Yoshimoto M
Department Of Computer Science And Systems Engineering Kobe University
-
Yamada A
Wireless Laboratories Ntt Docomo Inc.
-
Sato H
Ntt Microsystem Integration Laboratories
-
Matsumura T
System Lsi Development Center Mitsubishi Electric Corporation
-
Shimada Toshiaki
The Authors Are With Information Technology R&d Center Mitsubishi Electric Corporation
-
Yoshida Toyohiko
The Authors Are With System Lsi Development Center Mitsubishi Electric Corporation
-
Tsuchihashi K
The Authors Are With Kita-itami Works Mitsubishi Electric Corporation
-
Takata Hidehiro
The Authors Are With Electric Devices Design Center Mitsubishi Electric Engineering Corporation
関連論文
- Expression of a Novel 90-kDa Protein, Lsd90, Involved in the Metabolism of Very Long-chain Fatty Acid-containing Phospholipids in a Mitosis-defective Fission Yeast Mutant
- Waveguide-Integrated Si Nano-Photodiode with Surface-Plasmon Antenna and its Application to On-chip Optical Clock Distribution
- A Study on the Design and Properties of an SiON/SiO_2 Waveguide : The Effect of the Substrate on Propagation Loss
- Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
- A Sub 1-V L-Band Low Noise Amplifier SOI CMOS(Special Section on Analog Circuit Techniques and Related Topics)
- A CAD-Compatible SOI-CMOS Gate Array Using 0.35 μm Partially-Depleted Transistors (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Analyses of the Radiation-Caused Characteristics Change in SOI MOSFETs Using Field Shield Isolation
- Suppression of Self-Heating in Hybrid Trench Isolated SOI MOSFETs with Poly-Si plug and W plug
- LSI on-chip optical interconnection with Si nano-photonics
- Spectral responsivity of Ge pin photodiodes on silicon-on-insulator via selective epitaxial growth (光エレクトロニクス)
- Compact and polarization-independent variable optical attenuator based on a silicon wire waveguide with a carrier injection structure (Special issue: Solid state devices and materials)
- Low-loss silicon oxynitride waveguides and branches for the 850-nm-wavelength region (Special issue: Microoptics)
- Polarization splitter and rotator for polarization diversity system in silicon-based micro-photonic circuits (光エレクトロニクス)
- Photonic-Band-Gap Waveguides and Resonators in SOI Photonic Crystal Slabs(Photonic Crystals and Their Device Applications)
- Microphotonics Devices Based on Silicon Wire Waveguiding System(Photonic Crystals and Their Device Applications)
- An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
- A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
- Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
- Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
- An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
- Fast optical power stabilization using a germanium photodiode and a silicon variable optical attenuator integrated on a silicon photonic platform (レーザ・量子エレクトロニクス)
- Fast optical power stabilization using a germanium photodiode and a silicon variable optical attenuator integrated on a silicon photonic platform (光エレクトロニクス)
- Fast optical power stabilization using a germanium photodiode and a silicon variable optical attenuator integrated on a silicon photonic platform (フォトニックネットワーク)
- A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
- Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Random Access Memories (DRAMs)
- Estimation of Carrier Suppression by High-Energy Boron-Implanted Layer for Soft Error Reduction
- VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding(Low-Power System LSI, IP and Related Technologies)
- A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU(Low-Power System LSI, IP and Related Technologies)
- Microbeam Line of MeV Heavy Ions for Materials Modification and In-Situ Analysis : Beam-Induced Physics and Chemistry
- Microbeam Line of MeV Heavy Ions for Materials Modification and In-Situ Analysis
- Focused High-Energy Heavy Ion Beams
- Red Blood Cells Highly Express Type I Platelet-Activating Factor-Acetylhydrolase (PAF-AH) Which Consists of the α_1/α_2 Complex
- Regulation of Activities of Cytidine 5'-Diphospho-Choline : 1-O-Alkyl-2-Acetyl-sn-Glycerol Cholinephosphotransferase, an Enzyme Responsible for de novo Synthesis of Platelet-Activating Factor, by Membrane Phospholipids
- Pineal Gland (Melatonin) Affects the Parturition Time, but not Luteal Function and Fetal Growth, in Pregnant Rats
- Changes in Telomerase Activity in Experimentally Induced Atretic Follicles of Immature Rats
- Role of transient hyperprolactinemia in the late follicular phase of the gonadotropin-stimulated cycle
- Alterations in Nitrate/Nitrite and Nitric Oxide Synthase in Preovulatory Follicles in Gonadotropin-Primed Immature Rat
- An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
- Effect of Post-Growth Annealing on Morphology of Ge Mesa Selectively Grown on Si
- Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
- LSI On-Chip Optical Interconnection with Si Nano-Photonics
- A Monoclonal Antibody, 3A10, Recognizes a Specific Amino Acid Sequence Present on a Series of Developmentally Expressed Brain Proteins
- A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
- VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A Dependable SRAM with 7T/14T Memory Cells
- A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
- Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
- Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
- Impact of Body Bias Controlling in Partially Depleted SOI Devices with Hybrid Trench Isolation Technology
- A 90nm-node SOI Technology for RF Applications
- 23-P-06 Nano Crystalline and Smooth Surface Epilayer Formations of 3C-SiC at Low Temperatures Using Energetic Ions
- A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
- A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
- Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
- A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
- Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
- Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
- A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
- A Highly Parallel DSP Architecture for Image Recognition
- Evaluation of EMI Reduction Effect of Guard Traces Based on Imbalance Difference Model
- Increase of Common-Mode Radiation due to Guard Trace Voltage and Determination of Effective Via-Location
- A Prediction Method of Common-Mode Excitation on a Printed Circuit Board Having a Signal Trace near the Ground Edge(Electromagnetic Compatibility (EMC))
- A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
- A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
- A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
- A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
- A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
- Studies on the effects of initial injection doses of follicle stimulating hormone on the pregnancy and the ovarian hyperstimulation syndrome incidence in polycystic ovarian syndrome patients
- A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video (Special Issue on Multimedia, Analog and Processing LSIs)
- Development of time-to-digital converter IC for laser radar
- A CMOS Time-to-Digital Converter LSI with Half-Nanosecond Resolution Using a Ring Gate Delay Line (Special Issue on ASICs for Automotive Electronics)
- Common-Mode-Current Generation Caused by Difference of Unbalance of Transmission Lines on a Printed Circuit Board with Narrow Ground Pattern(Special Issue on Recent Progress in Electromagnetic Compatibility Technology)
- Prediction of Far-Field EMI Spectrum of Differential Mode Emission from a Digital PCB by Near-Field Measurement
- Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
- A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor(Special Issue on Novel VLSI Processor Architectures)
- An Objective Measure Based on an Auditory Model for Assessing Low-Rate Coded Speech
- A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
- A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply (Special Section on Low-Power and Low-Voltage Integrated Circuits)
- Transient Analysis of Switched Current Source
- A Dual-Issue RISC Processor for Multimedia Signal Processing(Special Issue on Novel VLSI Processor Architectures)
- Suppression of Guard-Trace Resonance by Matched Termination for Reducing Common-Mode Radiation
- Calculation of Common-Mode Radiation from Single-Channel Differential Signaling System Using Imbalance Difference Model
- An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set(Special Section on Digital Signal Processing)
- A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder(Special Issue on Multimedia, Network, and DRAM LSIs)
- ULSI Realization of MPEG2 Realtime Video Encoder and Decoder : An Overview
- Monolithic Integration of a Silica-Based Arrayed Waveguide Grating Filter and Silicon Variable Optical Attenuators Based on p--i--n Carrier-Injection Structure
- Fast Optical Power Stabilization using a Germanium Photodiode and a Silicon Variable Optical Attenuator Integrated on a Silicon Photonic Platform
- Fast optical power stabilization using a germanium photodiode and a silicon variable optical attenuator integrated on a silicon photonic platform (レーザ・量子エレクトロニクス)
- Fast optical power stabilization using a germanium photodiode and a silicon variable optical attenuator integrated on a silicon photonic platform (光エレクトロニクス)
- Fast optical power stabilization using a germanium photodiode and a silicon variable optical attenuator integrated on a silicon photonic platform (フォトニックネットワーク)
- A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
- VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
- A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
- Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
- A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
- 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
- Integration of Silicon Nano-Photonic Devices for Telecommunications
- A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
- A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme