ULSI Realization of MPEG2 Realtime Video Encoder and Decoder : An Overview

スポンサーリンク

概要

• 論文の詳細を見る

• This paper will describe an overview on several design issues and solutions for the realization of MPEG2 encoder amp decoder LSIs. ULSI technology and video-coding specific design have been able to actualize an MPEG2 encoder amp decoder LSI with realtime capability, flexibility and cost effectiveness, though MPEG2 processing at MP @ ML (Main Profile and Main Level) requires an enormous computaion power of 10-200 GOPS depending on the motion estimation algorithm and a search range. Video coding processors, whose performance has been enhanced at the rate of one order per 3 years, have reached the performance level required to implement MPEG2 encoding using multiple chip configuration. This has been achieved by a hybrid architecture with video-oriented RISC and hardware engine optimized for coding algorithms. Intensive circuit optimization was carried out for transform coding such as DCT and predictive coding with motion estimation. Now cost effective MPEG2 decoders have begun to penetrate the multimedia market. There are two main design issues. One is the architectural and circuit design which minimizes the silicon area and power dissipation. The other is external DRAM control which makes use of DRAM storage and band width efficiently to reduce the system cost. Also future trends in a deep submicron era will be discussed. A single chip MPEG2 MP @ ML encoder is expected to appear in the 0.25 micron era at the latest. An MPEG2 MP @ ML decoder could be compressed to an area of about 25 mm^2.

• 社団法人電子情報通信学会の論文
• 1995-12-25

著者

• Uramoto Shin-Ichi

  Mitsubishi Electric Corporation

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• ISHIHARA Kazuya

  System LSI Development Center,Mitsubishi Electric Corporation

• MATSUMURA Tetsuya

  System LSI Development Center,Mitsubishi Electric Corporation

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Nakagawa S

  Omron Corp. Information Technol. Res. Center Kyoto‐shi Jpn

• Ishihara Kazuya

  System Lsi Development Center Mitsubishi Electric Corporation

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• NAKAGAWA Shin-ichi

  the System LSI Division, Mitsubishi Electric Corporation

• Matsumura T

  System Lsi Development Center Mitsubishi Electric Corporation

• Nakagawa S

  Communications Res. Lab. Koganei‐shi Jpn

• Nakagawa Shin-Ichi

  Mitsubishi Electric Corporation

• Matsumura Tetsuya

  Mitsubishi Electric Corporation

• Ishihara Kazuya

  Mitsubishi Electric Corporation

関連論文

• An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
• A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
• Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
• An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
• VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding(Low-Power System LSI, IP and Related Technologies)
• A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU(Low-Power System LSI, IP and Related Technologies)
• An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
• Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
• A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
• VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
• A Dependable SRAM with 7T/14T Memory Cells
• A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
• Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
• Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
• An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
• A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
• A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
• Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
• A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
• Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
• Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
• A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
• A Highly Parallel DSP Architecture for Image Recognition
• A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
• A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
• A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
• A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
• A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
• A Variational Approach to Understanding the Ground State of a Square-Lattice Heisenberg Antiferromagnet
• Addendum to the Paper on UDRVB in One-Dimensional Spin-1/2 Heisenberg Systems with Frustration
• Exact Solution of the Ground State for Uniformly Distributed RVB in One-Dimensional Spen-1/2 Heisenberg Systems with Frustration
• A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video (Special Issue on Multimedia, Analog and Processing LSIs)
• Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE802.11e WLANs(Network)
• Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
• Future Technological and Economic Prospects for VLSI (Special Issue on LSI Memories)
• A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor(Special Issue on Novel VLSI Processor Architectures)
• A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
• An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set(Special Section on Digital Signal Processing)
• A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder(Special Issue on Multimedia, Network, and DRAM LSIs)
• ULSI Realization of MPEG2 Realtime Video Encoder and Decoder : An Overview
• A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
• A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
• Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
• A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
• 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
• A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

もっと見る 閉じる

スポンサーリンク