VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, <Special Section> VLSI Design Technology in the Sub-100nm Era)

概要

論文の詳細を見る
An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables highthroughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for GIF 30fr/s with 189 MHz clock frequency. Its estimated core size is 6.02×5.33mm^2 with six-metal 90-nm CMOS technology.
社団法人電子情報通信学会の論文