A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
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概要
- 論文の詳細を見る
As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Moreover, the process variation strongly affects network-on-chips (NoCs) that have a synchronous network across the chip. Therefore, its network frequency is degraded. We propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively on a processor core basis, corresponding to the process variation. It can increase the network frequency, which is limited by the process variation in a conventional router. Furthermore, we propose a variable-cycle pipeline adaptive routing (VCPAR) method with VAVCR; the proposed VCPAR can reduce packet latency and has tolerance to network congestion. The total execution time reduction of the proposed VAVCR with VCPAR is 15.7%, on average, for five task graphs.
- The Institute of Electronics, Information and Communication Engineersの論文
- 2012-04-01
著者
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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YOSHIMOTO Masahiko
Kobe University
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Kawaguchi Hiroshi
Department Of Computer Science And Systems Engineering Kobe University
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Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
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NAKATA Yohei
Kobe University
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