An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video

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概要

• 論文の詳細を見る

• This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a Gradient Descent Search (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SlMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50mm × 3.35mm area using 0.13μm CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.

• 社団法人電子情報通信学会の論文
• 2003-04-01

著者

• Kato Ai

  The Authors Are With The Faculty Of Engineering Kanazawa University

• Miyama Masayuki

  Kanazawa University Graduate School Of Natural Science & Technology

• Miyama M

  Graduate School Of Natural Science And Technology Kanazawa University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• YOSHIMOTO Masahiko

  The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation

• MIYAMA Masayuki

  The authors are with the Faculty of Engineering, Kanazawa University

• TOOYAMA Osamu

  The authors are with the Faculty of Engineering, Kanazawa University

• TAKAMATSU Naoki

  The authors are with the Faculty of Engineering, Kanazawa University

• KODAKE Tsuyoshi

  The authors are with the Faculty of Engineering, Kanazawa University

• NAKAMURA Kazuo

  The authors are with the Faculty of Engineering, Kanazawa University

• MIYAKOSHI Junichi

  The authors are with the Faculty of Engineering, Kanazawa University

• IMAMURA Kousuke

  The authors are with the Faculty of Engineering, Kanazawa University

• HASHIMOTO Hideo

  The authors are with the Faculty of Engineering, Kanazawa University

• KOMATSU Satoshi

  The author is with VLSI Design and Education Center, The University of Tokyo

• YAGI Mikio

  The authors are with the Faculty of Engineering, Kobe University

• MORIMOTO Masao

  The authors are with the Faculty of Engineering, Kobe University

• TAKI Kazuo

  The authors are with the Faculty of Engineering, Kobe University

• Tooyama Osamu

  The Authors Are With The Faculty Of Engineering Kanazawa University

• Morimoto Masao

  The Authors Are With The Faculty Of Engineering Kobe University

• Kodake Tsuyoshi

  The Authors Are With The Faculty Of Engineering Kanazawa University

• Takamatsu Naoki

  The Authors Are With The Faculty Of Engineering Kanazawa University

• Imamura Kousuke

  The Dept. Of Electrical & Electronic System Kanazawa University

• Komatsu Satoshi

  The Author Is With Vlsi Design And Education Center The University Of Tokyo

• MIYAKOSHI Junichi

  Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Yagi Mikio

  The Authors Are With The Faculty Of Engineering Kobe University

• Taki Kazuo

  The Authors Are With The Faculty Of Engineering Kobe University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• Hashimoto H

  The Dept. Of Electrical & Electronic System Kanazawa University

• Hashimoto Hideo

  The Dept. Of Electrical & Electronic System Kanazawa University

• Nakamura Kazuo

  The Authors Are With The Faculty Of Engineering Kanazawa University

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