A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
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概要
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This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - Vtn and therefore saves the active power in the half-selected columns (where Vtn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125°C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the Vtn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-µW/MHz writing energy and 72.8-µW leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 µW/MHz (12.9 pJ/access) at a supply voltage of 0.5V and operating frequency of 6.25MHz in a 50%-read/50%-write operation.
- The Institute of Electronics, Information and Communication Engineersの論文
- 2012-04-01
著者
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Yoshimoto Masahiko
Mitsubishi Electric Corporation
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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OKUMURA Shunsuke
Kobe University
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MORITA Yasuhiro
Kobe University
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Suzuki Toshikazu
Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.
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Kawaguchi Hiroshi
Department Of Computer Science And Systems Engineering Kobe University
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Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
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Yoshimoto M
Department Of Computer Science And Systems Engineering Kobe University
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Miyano Shinji
Semiconductor Technology Academic Research Center
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YOSHIMOTO Shusuke
Kobe University
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YOSHIMOTO Masahiko
JST, CREST
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Suzuki Toshikazu
Semiconductor Technology Academic Research Center (starc)
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TERADA Masaharu
Kobe University
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