High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)

概要

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Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level V_pp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the V_pp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5μm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at V_cc=3.3V, and also even at V_cc=1.8V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.
社団法人電子情報通信学会の論文
1994-08-25