A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_<th>) Variation(<Special Section>Novel Device Architectures and System Integration Technologies)

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概要

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• Fundamental limitation on assisting a write margin (WRTM) by reducing the cell terminal bias (VDDM) has been made clear for the first time and the new cell terminal biasing scheme featuring a differential VDDM (Diff-VDDM) control has been proposed to address the issues which the conventional schemes proposed so far can not overcome. Since Diff-VDDM biasing scheme can meet the both of the requirements simultaneously of 1) reducing drivability for the PMOS load transistor on the "Low" written bit-line (BL) side, and 2) increasing drivability for the other side PMOS for a write recovery, it can provide a lower minimum operating voltage (V_<dd->min) for the write operation even if considering a sufficiently-large random threshold voltage (V_<th>) variations. The following points have been shown based on an actual 65nm CMOS device variation data and the implemented layout data that 1) V_<dd->min for the write operation can be lowered from V_<dd>=1.1V down to 0.8V when considering a 4-sigma (σ) variation, 2) the write recovery time can be reduced by 92% and 70% that for the conventional schemes at V_<dd>=0.7V and 1.0V, respectively, and 3) WRTM defined by the percentage (%) of the required (BL pull-down level/V_<dd>) to flip the cell nodes for the write operation can be relaxed by 2.6-fold and 1.4-fold that for the conventional schemes at V_<dd>=0.75V and 1.0V, respectively. As an actual implementation in a 65nm CMOS, a 32-kbit single-port SRAM macro design and the measured butterfly curves have been demonstrated.

• 社団法人電子情報通信学会の論文
• 2006-11-01

著者

• YAMAUCHI Hiroyuki

  Faculty of Information Engineering, Fukuoka Institute of Technology

• Suzuki Toshikazu

  Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Yamauchi Hiroyuki

  Faculty Of Information Engineering Dept. Of Computer Science And Engineering Fukuoka Institute Of Te

• Yamauchi H

  Faculty Of Information Engineering Fukuoka Institute Of Technology

• YAMAGAMI Yoshinobu

  Corporate SLSI Development Div., Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

• Yamagami Yoshinobu

  Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Suzuki Toshikazu

  Semiconductor Technology Academic Research Center (starc)

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• A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_) Variation(Novel Device Architectures and System Integration Technologies)
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