A Rewritable CMOS-FUSE for System-on-Chip with a Defferential Cell Architecture in a 0.13μm CMOS Logic Process(CMOS Fuse)(<Special Section>New Era of Nonvolatile Memories)

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This paper describes a 0.13μm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SOC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SOC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories(50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of ≦200 kbit for the SOC occupied the logic area of 40mm^2. 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13μm devices. Based on the measured data retention characteristics at 300℃, 250℃, and 200℃, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105℃. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105℃ can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant V_l, shifts (≦140mV and ≦200mV) were observed even after applying surge stress of +2200V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.
社団法人電子情報通信学会の論文
2004-10-01

A Rewritable CMOS-FUSE for System-on-Chip with a Defferential Cell Architecture in a 0.13μm CMOS Logic Process(CMOS Fuse)(<Special Section>New Era of Nonvolatile Memories)

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