A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses(Memory,<Special Section>Low-Power, High-Speed LSIs and Related Technologies)

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概要

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• A guarantee obligation of keeping a Static-Noise-Margin (SNM), a Write-Margin (WRTM), and a cell current (Icell) even against a simultaneous Read/Write (R/W) disturbed access at the same column is required for a 1R/1W (1R/1W) SRAM. We have verified that it is difficult for the previously proposed techniques so far to meet all the requirements simultaneously without any decrease in Icell or any significant area penalty. In order to address this issue, a new cell design technique for the 1R/1W SRAM cell with 8Tr's has been proposed and demonstrated in a 65nm CMOS technology. It has been shown that Icell in the R/W disturbed column can be increased by 77% and 195% at V_<dd>=0.9V and 0.6V, respectively, and a cell size can be reduced by 15%, compared with the conventional column-based cell power-terminal bias (VDDM) control assuming that the same Icell of 9μA at V_<dd>=0.9V has to be provided. Compared with the conventional scheme, it has been found that the proposed Write-Bit-Line precharge level (VWBL) control and column-based cell source-terminal bias (VSSM) control can provide a 1.45-times larger SNM for Write-Word-Line (WWL) disturbed cells and a 1.7-fold larger WRTM while keeping the same Icell, respectively.

• 社団法人電子情報通信学会の論文
• 2007-04-01

著者

• YAMAUCHI Hiroyuki

  Faculty of Information Engineering, Fukuoka Institute of Technology

• Suzuki Toshikazu

  Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Yamauchi Hiroyuki

  Faculty Of Information Engineering Dept. Of Computer Science And Engineering Fukuoka Institute Of Te

• Yamauchi H

  Faculty Of Information Engineering Fukuoka Institute Of Technology

• YAMAGAMI Yoshinobu

  Corporate SLSI Development Div., Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

• Yamagami Yoshinobu

  Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Suzuki Toshikazu

  Semiconductor Technology Academic Research Center (starc)

関連論文

• A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI(Semiconductor Materials and Devices)
• 0.3-1.5V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier(Memory, Low-Power LSI and Low-Power IP)
• An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's(Special Issue on the 1994 VLSI Circuits Symposium)
• A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's
• High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)
• A Rewritable CMOS-FUSE for System-on-Chip with a Defferential Cell Architecture in a 0.13μm CMOS Logic Process(CMOS Fuse)(New Era of Nonvolatile Memories)
• A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_) Variation(Novel Device Architectures and System Integration Technologies)
• A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs (Special Issue on Low-Power and High-Speed LSI Technologies)
• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

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