YAMAUCHI Hiroyuki | Faculty of Information Engineering, Fukuoka Institute of Technology

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著作論文

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI(Semiconductor Materials and Devices)
0.3-1.5V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier(Memory, Low-Power LSI and Low-Power IP)
An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's(Special Issue on the 1994 VLSI Circuits Symposium)
A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's
High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)
A Rewritable CMOS-FUSE for System-on-Chip with a Defferential Cell Architecture in a 0.13μm CMOS Logic Process(CMOS Fuse)(New Era of Nonvolatile Memories)
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses(Memory,Low-Power, High-Speed LSIs and Related Technologies)
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_) Variation(Novel Device Architectures and System Integration Technologies)
A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs (Special Issue on Low-Power and High-Speed LSI Technologies)

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