0.3-1.5V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier(Memory, <Special Section>Low-Power LSI and Low-Power IP)

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概要

• 論文の詳細を見る

• This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V_<dd>=0.3-1.5V). In the conventional SRAMs, a wiring-replica with replicamemory-cell (RMC) to trace the delay of memory core is used for this purpose. Introducing a wiring-replica control provides the better tracing capability in the wide range of V_<dd> above 0.5V than those of using the control with logic-gate-delay. However, as V_<dd> is reduced below 0.5V and gets close to the threshold voltage (V_<th>) of transistors, the access-timing fluctuation resulting from the variation in memory-cell-transistor-drain current (I_d) is intolerably increased. As a result, the conventional control is no longer effective in such a low-voltage operation because the RMC can not replicate the variation in transistor-drain current (I_d) and V_<th> of the memory-cells (MCs). Thus, to trace the access-timing fluctuation caused by the variation in I_d and V_<th> is the prerequisite for the SRAM control in the range of V_<dd>=0.3-1.5V. To solve this issue, we have proposed new accesscontrol scheme as follows ; 1) a write-replica circuit with an asymmetrical memory cell (WRAM) making it possible to replicate the variation in I_d and V_<th> for the write-access timing control, and 2) a source-level-adjusted direct-sense-amplifier (SLAD) to accelerate the read-access-timing even in low V_<dd>. These circuit techniques were implemented in a 32-Kbit SRAM in four-metal 130-nm CMOS process technology, and have been verified a low-voltage operation of 0.3V which has not ever reported with 6.8MHz. Moreover it operated in wide-voltage up to 1.5V with 960MHz. The required 27MHz operation for mobile applications has been demonstrated at 0.4V which is 6-times faster than the previous reports. The WRAM scheme enabled the write operation even at 0.3V. And the access time which can be restricted by the slow tail bits of MCs has been accelerated by 73% to 140 nsec at 0.3V by using SLAD scheme.

• 2005-04-01

著者

• YAMAUCHI Hiroyuki

  Faculty of Information Engineering, Fukuoka Institute of Technology

• Suzuki Toshikazu

  Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Yamauchi Hiroyuki

  Faculty Of Information Engineering Dept. Of Computer Science And Engineering Fukuoka Institute Of Te

• Yamauchi H

  Faculty Of Information Engineering Fukuoka Institute Of Technology

• YAMAUCHI Hiroyuki

  Matsushita Electric Industrial Co., Ltd.

• YAMAGAMI Yoshinobu

  Corporate SLSI Development Div., Semiconductor Company, Matsushita Electric Industrial Co., Ltd.

• SUZUKI Toshikazu

  Matsushita Electric Industrial Co., Ltd.

• YAMAGAMI Yoshinobu

  Matsushita Electric Industrial Co., Ltd.

• HATANAKA Ichiro

  Matsushita Electric Industrial Co., Ltd.

• SHIBAYAMA Akinori

  Matsushita Electric Industrial Co., Ltd.

• AKAMATSU Hironori

  Matsushita Electric Industrial Co., Ltd.

• Shibayama Akinori

  Matsushita Electric Industrial Co. Ltd.

• Hatanaka Ichiro

  Matsushita Electric Industrial Co. Ltd.

• Akamatsu Hironori

  Corporate Semiconductor Development Division Matsushita Electric Industrial Co. Ltd.

• Yamagami Yoshinobu

  Corporate Slsi Development Div. Semiconductor Company Matsushita Electric Industrial Co. Ltd.

• Akamatsu Hironori

  Semiconductor Research Center Sl24 Matsushita Electric Industrial Co. Ltd.

• Suzuki Toshikazu

  Semiconductor Technology Academic Research Center (starc)

関連論文

• A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI(Semiconductor Materials and Devices)
• 0.3-1.5V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier(Memory, Low-Power LSI and Low-Power IP)
• An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's(Special Issue on the 1994 VLSI Circuits Symposium)
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• High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM (Special Section on High Speed and High Density Multi Functional LSI Memories)
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• A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses(Memory,Low-Power, High-Speed LSIs and Related Technologies)
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