A 168-mW 2.4×-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI
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概要
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This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). It features a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40nm CMOS technology, occupies 1.77mm × 2.18mm containing 2.52 M transistors for logic and 4.29Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3MHz), 48.5% power consumption reduction (74.14mW) for 60 k-Word real-time continuous speech recognition compared to the previous work while 30% of the area is saved with recognition accuracy of 90.9%. This chip can maximally process 2.4× faster than real-time at 200MHz and 1.1V with power consumption of 168mW. By increasing the beam width, better recognition accuracy (91.45%) can be achieved. In that case, the power consumption for real-time processing is increased to 97.4mW and the max-performance is decreased to 2.08× because of the increased computation workload.
著者
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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YOSHIMOTO Masahiko
Kobe University
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SUGAHARA Takanobu
Kobe University
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HE Guangji
Kobe University
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IZUMI Shintaro
Kobe University
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MIYAMOTO Yuki
Kobe University
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