Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes

スポンサーリンク

概要

• 論文の詳細を見る
• 2012-01-01

著者

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• Ohta Chikara

  Department Of Computer Science And Systems Engineering Kobe University

• MORITA Yasuhiro

  Kobe University

• Kawaguchi Hiroshi

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Izumi Shintaro

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• Sakai Yasuharu

  Department Of Computer Science And Systems Engineering Kobe University

• Matsuda Takashi

  Department Of Computer Science And Systems Engineering Kobe University

• Takeuchi Takashi

  Department Of Computer Science And Systems Engineering Kobe University

• Kawaguchi Hiroshi

  The Graduate School Of Science And Technology Kobe University

• MATSUDA Takashi

  the Graduate School of Science and Technology, Kobe University

• IZUMI Shintaro

  the Graduate School of Science and Technology, Kobe University

• SAKAI Yasuharu

  the Graduate School of Science and Technology, Kobe University

• TAKEUCHI Takashi

  the Graduate School of Science and Technology, Kobe University

• FUJIWARA Hidehiro

  the Graduate School of Science and Technology, Kobe University

• OHTA Chikara

  the Graduate School of Science and Technology, Kobe University

• YOSHIMOTO Masahiko

  the Graduate School of Science and Technology, Kobe University

• Fujiwara Hidehiro

  The Graduate School Of Science And Technology Kobe University

• Ohta Chikara

  The Graduate School Of Science And Technology Kobe University

• Matsuda Takashi

  The Graduate School Of Science And Technology Kobe University

• Takeuchi Takashi

  The Graduate School Of Science And Technology Kobe University

• Izumi Shintaro

  The Graduate School Of Science And Technology Kobe University

関連論文

• Synthesis and Activity of a New Type of Anti-HIV Agents, Conjugate of HIV Protease Inhibitor with Reverse Transcriptase Inhibitor
• An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
• A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
• Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
• An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
• VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding(Low-Power System LSI, IP and Related Technologies)
• A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU(Low-Power System LSI, IP and Related Technologies)
• An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
• Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
• GDS-14 OPTIMUM DESIGN OF TOOTH-SURFACE MODIFICATION FOR AXIS-DISPLACED CYLINDRICAL GEARS(GEAR DESIGN AND SYNTHESIS)
• A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
• VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
• Scheduling Algorithm to Provide QoS over a Shared Wireless Link
• Scheduling Algorithms for Maximizing Throughput with Zero-Forcing Beamforming in a MIMO Wireless System
• A Dependable SRAM with 7T/14T Memory Cells
• A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
• Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
• Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
• An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
• A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
• A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
• Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
• A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
• Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
• Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
• A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
• A Highly Parallel DSP Architecture for Image Recognition
• A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
• A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
• A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
• A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
• A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
• A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video (Special Issue on Multimedia, Analog and Processing LSIs)
• Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE802.11e WLANs(Network)
• A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
• Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
• Future Technological and Economic Prospects for VLSI (Special Issue on LSI Memories)
• Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_/V_ and Micro-V_-Hopping (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
• Determination of Elastic Constants of K_2[PtCl_4] by Ultrasonic Measurements and Confirmation of Angular Dependence of Their Component by X-Ray Diffuse Scattering
• Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines(Physical Design,VLSI Design and CAD Algorithms)
• Trends of On-Chip Interconnects in Deep Sub-Micron VLSI (Interconnect Technique, VLSI Design Technology in the Sub-100nm Era)
• A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
• An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set(Special Section on Digital Signal Processing)
• A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder(Special Issue on Multimedia, Network, and DRAM LSIs)
• ULSI Realization of MPEG2 Realtime Video Encoder and Decoder : An Overview
• Phase Assignment Algorithm Based on Traffic Measurement for Real-Time MPEG Sources in ATM Networks
• B-5-110 Proposal of Distributed Resource Allocation Scheme for Wireless Networks
• Macrocell batch resource allocation for a co-channel macrocell/femtocell network (無線通信システム)
• Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques
• Experimental Study of Dynamic Specific Heat Capacity of Protein Aqueous Solutions
• Measurement of Dynamic Specific Heat Capacity of Lysozyme Crystals
• Ultrasonic Study of K_2SeO_4 in the Temperature Range of the Incommensurate Phase Transition
• Nonlinearity of the Dielectric Constant of Ferroelectric Triglycine Sulfate
• Specific Heat Capacity of Pb_Ge_xTe at Their Structural Phase Transitions
• Multibiofeedback Therapy for Drug Discontinuation in Panic Disorder Patients : A Pilot Study
• Biofeedback therapy using MULTI feedback for patients with psychosomatic disorder
• Microscopic Origin of the Ferroelastic Phase Transition in LiNH_4C_4H_4O_6・H_2O
• A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
• 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme (System LSI Design Methodology Vol.5)
• A Molecular Dynamics Study of an Exothermically Reacting System;A Detonation Phenomenon
• Ultrasonic Velocity Fluctuation in Muscle : General Acoustics
• A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
• Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
• A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
• 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
• A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
• A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
• A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
• A 168-mW 2.4×-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI
• An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter
• Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
• A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops
• Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
• A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI
• Fair Partitioning of the Downlink Resources of an OFDMA-Based Multi-User Multi-Tier Cellular Network Using Fractional Frequency Reuse
• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
• Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell
• A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells
• A Sub-100mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video
• A 168-mW 2.4×-Real-Time 60-k Word Continuous Speech Recognition Processor VLSI

もっと見る 閉じる

スポンサーリンク