A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops
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概要
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We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61dB is achievable at an input bandwidth of 500kHz and a sampling rate of 16MHz, where the respective area and power are 700µm2 and 281µW.
著者
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IZUMI Shintaro
Department of Computer Science and Systems Engineering, Kobe University
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Izumi Shintaro
Department Of Computer Science And Systems Engineering Kobe University
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Kawaguchi Hiroshi
Department Of Applied Chemistry Faculty Of Engineering Utsunomiya University
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Konishi Toshihiro
Department Of Computer And Systems Engineering Kobe University
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Yoshimoto Masahiko
Department of Computer and Systems Engineering, Kobe University
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OKUNO Keisuke
Department of Computer Science and Systems Engineering, Kobe University
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