Yoshimoto Masahiko | Department of Computer and Systems Engineering, Kobe University

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概要

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著作論文

Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
A power-variation model for sensor node and the impact against life time of wireless sensor networks
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter
A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops
A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

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