Yoshimoto Masahiko | Department of Computer and Systems Engineering, Kobe University
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概要
- Yoshimoto Masahikoの詳細を見る
- 同名の論文著者
- Department of Computer and Systems Engineering, Kobe Universityの論文著者
関連著者
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Yoshimoto Masahiko
Department of Computer and Systems Engineering, Kobe University
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Yoshimoto Masahiko
Department Of Computer Science And Systems Engineering Kobe University
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Kawaguchi Hiroshi
Department Of Applied Chemistry Faculty Of Engineering Utsunomiya University
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Yoshimoto Masahiko
Mitsubishi Electric Corporation
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Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
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Yoshimoto M
Department Of Computer Science And Systems Engineering Kobe University
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YOSHIMOTO Masahiko
Department of Computer Science and Systems Engineering, Kobe University
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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Kawaguchi Hiroshi
Department Of Computer Science And Systems Engineering Kobe University
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Izumi Shintaro
Department Of Computer Science And Systems Engineering Kobe University
著作論文
- Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
- A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
- A power-variation model for sensor node and the impact against life time of wireless sensor networks
- A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
- A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
- Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
- A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
- A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
- A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
- An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter