Yoshimoto Masahiko | Department Of Computer Science And Systems Engineering Kobe University

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概要

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著作論文

Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
A Dependable SRAM with 7T/14T Memory Cells
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
A power-variation model for sensor node and the impact against life time of wireless sensor networks
A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

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