MURACHI Yuichiro | Graduate School of Science and Technology, Kobe University

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概要

• 同名の論文著者
• Graduate School of Science and Technology, Kobe Universityの論文著者

関連著者

• Kawaguchi Hiroshi

  Graduate School of Engineering, Kobe University

• Yoshimoto Masahiko

  Graduate School of Engineering, Kobe University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• MIYAKOSHI Junichi

  Kobe University

• MORITA Yasuhiro

  Kobe University

• Kawaguchi Hiroshi

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• ISHIHARA Tomokazu

  Kobe University

• MIYAKOSHI Junichi

  Graduate School of Science and Technology, Kobe University

• MURACHI Yuichiro

  Graduate School of Science and Technology, Kobe University

• ISHIHARA Tomokazu

  Graduate School of Science and Technology, Kobe University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• Miyama Masayuki

  Graduate School of Natural Science, Kanazawa University

• Miyama Masayuki

  Kanazawa University Graduate School Of Natural Science & Technology

• Miyama M

  Graduate School Of Natural Science And Technology Kanazawa University

• Miyama Masayuki

  Graduate School Of Natural Science And Technology Kanazawa Univ.

• Matsuno Tetsuro

  Kanazawa University Graduate School Of Natural Science & Technology

• Matsuno Tetsuro

  Graduate School Of System Informatics Kobe University

• HAMAMOTO Masaki

  Kobe University

• IINUMA Takahiro

  Kobe University

• HAMAMOTO Masaki

  Graduate School of Science and Technology, Kobe University

• IINUMA Takahiro

  Graduate School of Science and Technology, Kobe University

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著作論文

• A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
• A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)

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