Kawaguchi Hiroshi | Graduate School of Engineering, Kobe University

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概要

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著作論文

Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential
A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential
Data-Intensive Sound Acquisition System with Large-scale Microphone Array
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme
Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
An FPGA Implementation of a HOG-based Object Detection Processor
Introducing Multiple Microphone Arrays for Enhancing Smart Home Voice Control

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