A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture

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概要

• 論文の詳細を見る

• We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW in a QCIF 15-fps sequence with one reference picture. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• Miyama Masayuki

  Graduate School of Natural Science, Kanazawa University

• Kawaguchi Hiroshi

  Graduate School of Engineering, Kobe University

• Yoshimoto Masahiko

  Graduate School of Engineering, Kobe University

• Miyama Masayuki

  Kanazawa University Graduate School Of Natural Science & Technology

• Miyama M

  Graduate School Of Natural Science And Technology Kanazawa University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Kawaguchi Hiroshi

  Kobe Univ. Kobe‐shi Jpn

• Miyama Masayuki

  Graduate School Of Natural Science And Technology Kanazawa Univ.

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• MIYAKOSHI Junichi

  Kobe University

• MORITA Yasuhiro

  Kobe University

• Matsuno Tetsuro

  Kanazawa University Graduate School Of Natural Science & Technology

• Matsuno Tetsuro

  Graduate School Of System Informatics Kobe University

• Kawaguchi Hiroshi

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• HAMAMOTO Masaki

  Kobe University

• IINUMA Takahiro

  Kobe University

• ISHIHARA Tomokazu

  Kobe University

• MIYAKOSHI Junichi

  Graduate School of Science and Technology, Kobe University

• MURACHI Yuichiro

  Graduate School of Science and Technology, Kobe University

• HAMAMOTO Masaki

  Graduate School of Science and Technology, Kobe University

• IINUMA Takahiro

  Graduate School of Science and Technology, Kobe University

• ISHIHARA Tomokazu

  Graduate School of Science and Technology, Kobe University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

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